1. Field of the Invention
The present invention relates to a flip-flop in current mode logic controlled by a transfer clock having a first differential amplifier with emitter-coupled transistors fed by a primary current source, and second and third differential amplifiers disposed in the collector circuits of the emitter-coupled transistors, whereby the transfer clock is applied to the base of the first transistor and the base of the second transistor is connected to a fixed potential.
2. Description of the Prior Art
Given flip-flop circuits constructed on the basis of current mode logic (ECL,CML), the circuit principle of series coupling or of series linkage is frequently employed (cf. "Der Fernmeldeingenieur", Vol. 27, No. 7, July 1973, pp. 19 and 20). For the purpose of a better understanding of the invention which shall be discussed below, a known, clock-controlled D flip-flop of this type which shall be referred to below is illustrated in FIG. 1 of the drawing.
A first differential amplifier having emitter-coupled transistors T1 and T2 is fed by a constant current source comprising a transistor T3 having a base connected to a first reference potential VR1 and an emitter resistor R1. A clock signal C level-shifted with the assistance of an emitter follower T0, R0 is applied to the base of the first transistor T1. The base of the second transistor T2 of the first differential amplifier is connected to a second reference potential VR2.
The emitters of the two transistors T4 and T5 of a second differential amplifier are connected to the collector of the transistor T1 of the first differential amplifier. The base of the transistor T4 forms a data input D for the information to be input into the flip-flop. The base of the third transistor T5 is connected to a third reference potential VR3.
A third differential amplifier having a pair of transistors T6 and T7 whose emitters are connected to the collector of the transistor T2 of the first differential amplifier. The transistor T6, whose base is likewise connected to the third reference potential VR3, has collector connected to the collector of the transistor T5 and to a load resistor R2 which it shares with the transistor T5 of the second differential amplifier. The voltage drop arising at the load resistor R2, in accordance with the respective switch state of the flip-flop and represents the stored information, finally determines the binary value of the output signal which is tapped at an output Q of the flip-flop which is additionally level-shifted by way of an emitter follower having a transistor T8 and an emitter resistor R3. The signal feedback required for the bistable behavior of the circuit arrangement occurs from the output Q to the base of the transistor T7 of the third differential amplifier.
A (positive) pulse at the clock input C renders the transistor T1 conductive. When a binary "1" is applied at the data input D at the same time, the current I1 supplies the constant current source flow through the transistor T4. The transistors T2 and T5 are turned off. Therefore, no current flows through the load resistor R2 and the output Q carries the binary value "1". At the end of the clock pulse at the input C, the transistor T1 transfers into its blocking condition and the transistor T2 becomes conductive. At the same time, the transistor T7 also becomes conductive, whereas the transistor T6 remains nonconductive. As a result, the signal level at the output Q likewise does not change. The information applied to the data input D is continuously stored. A change of the signal level at the data input D which may occur between two pulses of the transfer clock cannot take effect because the second differential amplifier with the transistors T4 and T5 is nonconductive because of the blockage of the transistor T1.
The input of a binary "0" to the data input D by a pulse fundamentally occurs in the same manner as that described for the input of the binary "1". Of course, the transistor T4 in the second differential amplifier is now first turned off and the transistor T5 is conductive. A voltage drop arises across the load resistor R2 and the output Q carries the lower signal level corresponding to a binary "0". Upon acceptance of the current I1 by the transistor T2 at the end of the clock pulse, therefore, the transistor T6 of the third differential amplifier becomes conductive so that the binary signal value "0" can continue to be tapped at the output Q of the flip-flop.
The transfer of a binary "0" to be stored from the second differential amplifier into the third differential amplifier, however, does not occur completely without interference. On the contrary, a short positive pulse (spike) arises at the output Q having a more or less large amplitude. The reason for this is that the current through the transistor T5 decreases faster than the rise of the current through the transistor T6. Therefore, the sum of the sub-currents does not remain constant.
A noise pulse at the output Q, however, cannot only lead to a false reaction of the following circuit arrangements but, rather, can also produce a misbehavior of the flip-flop, a loss of data.